CPU hardware information


I de her komandoer når vi bredt omkring. Lige fa CPU til harddisk, BIOS, mv.. God fornøjelse.

CPU-informationen indeholder detaljer om processoren, så som arkitekturen, leverandørens navn, model, antal kerner, hastighed på hver kerne osv. Der er ganske få kommandoer på Linux der kan vise disse oplysninger om cpu-hardware. Her vil jeg kort gennemgå nogle komandoer til dette brug.

/proc/cpuinfo


Filen / proc / cpuinfo indeholder detaljer om individuelle cpu kerner. Ved uddata kan bruges less eller cat for at splitte det op i mindre stykker.

$ less /proc/cpuinfo

processor : 0

vendor_id : GenuineIntel

cpu family : 6

model : 60

model name : Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

stepping : 3

microcode : 0x24

cpu MHz : 2819.192

cache size : 6144 KB

physical id : 0

siblings : 4

core id : 0

cpu cores : 4

apicid : 0

initial apicid : 0

fpu : yes

fpu_exception : yes

cpuid level : 13

wp : yes

For at tælle antallet af prcesenheder med grep og wc

$ cat /proc/cpuinfo | grep processor | wc -l

4

Få CPU Info ved hjælp af cat komandoen


Du kan se oplysningerne fra din system-CPU ved at se indholdet af / proc / cpuinfo-filen ved hjælp af cat-kommandoen

$ cat /proc/cpuinfo

processor : 0

vendor_id : GenuineIntel

cpu family : 6

model : 60

model name : Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

stepping : 3

microcode : 0x24

cpu MHz : 1370.933

cache size : 6144 KB

physical id : 0

siblings : 4

core id : 0

cpu cores : 4

apicid : 0

initial apicid : 0

fpu : yes

fpu_exception : yes

cpuid level : 13

wp : yes

Og meget mere

For at få en smule mere specifikt output, kan du anvende grep-kommandoen for at data , der matcher et regulært udtryk. Dette kan hjælpe dig med at vise leverandørens navn, modelnavn, antal processorer, antal kerner osv.

Se leverandør navn


$ cat /proc/cpuinfo | grep 'vendor' | uniq

vendor_id : GenuineIntel

Vis model navn


$ cat /proc/cpuinfo | grep 'model name' | uniq

model name : Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

Tæl antallet af procesenheder


$ cat /proc/cpuinfo | grep processor | wc -l

4

Vis individuelle kerner


$ cat /proc/cpuinfo | grep 'core id'

core id : 0

core id : 1

core id : 2

core id : 3

lscpu


lscpu er en lille og hurtig kommando, der ikke behøver nogen tilvalgsmuligheder. Det ville blot udskrive cpu hardware detaljer i et brugervenligt format.

$ lscpu

Arkitektur: x86_64

Op-tilstande for CPU: 32-bit, 64-bit

Byterækkefølge: Little Endian

CPU'er: 4

Tilkoblet cpu(er) liste: 0-3

Tråde per kerne: 1

Kerner per sokkel: 4

Sokler: 1

NUMA-knuder: 1

Leverandør-id: GenuineIntel

CPU-familie: 6

Model: 60

Modelnavn: Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz

Modelserie: 3

CPU MHz: 2948.658

CPU maks. MHz: 3600,0000

CPU min. MHz: 800,0000

BogoMIPS: 6399.40

Virtualisation: VT-x

L1d mellemlager: 32K

L1i mellemlager: 32K

L2 mellemlager: 256K

L3 mellemlager: 6144K

NUMA-knuder0 CPU'er: 0-3 Flag

Vis Device Information


Vis lagerenheder såsom harddiske, flashdrev etc. lsblk kommando bruges til at vise oplysninger om blok enheder.

$ lsblk

Hvis du vil se alle blok-enheder på dit system, så skal du inkludere -a flaget.

Vis USB Controllers Information


lsusb-kommandoen bruges til at vise oplysninger om USB-controllere og alle de enheder, der er forbundet med dem.

$ lsusb

Bus 002 Device 002: ID 8087:8000 Intel Corp.

Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Bus 006 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub

Bus 005 Device 002: ID 1d57:ad05 Xenta

Bus 005 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Bus 001 Device 002: ID 8087:8008 Intel Corp.

Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub

Bus 003 Device 003: ID 0bc2:331a Seagate RSS LLC

Bus 003 Device 002: ID 045e:07f8 Microsoft Corp. Wired Keyboard 600 (model 1576)

Bus 003 Device 004: ID 0bc2:331a Seagate RSS LLC

Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Du kan bruge -v flaget til at generere detaljerede oplysninger om hver USB-enhed.

lsusb -v

Her kun en del af outputtet

Bus 002 Device 002: ID 8087:8000 Intel Corp. Couldn't open device, some information will be missing Device Descriptor:

bLength                18
bDescriptorType         1
bcdUSB               2.00
bDeviceClass            9 Hub
bDeviceSubClass         0 
bDeviceProtocol         1 Single TT
bMaxPacketSize0        64
idVendor           0x8087 Intel Corp.
idProduct          0x8000 
bcdDevice            0.05
iManufacturer           0 
iProduct                0 
iSerial                 0 
bNumConfigurations      1
Configuration Descriptor:
  bLength                 9
  bDescriptorType         2
  wTotalLength           25
  bNumInterfaces          1
  bConfigurationValue     1
  iConfiguration          0 
  bmAttributes         0xe0
    Self Powered
    Remote Wakeup
  MaxPower                0mA
  Interface Descriptor:
    bLength                 9
    bDescriptorType         4
    bInterfaceNumber        0
    bAlternateSetting       0
    bNumEndpoints           1
    bInterfaceClass         9 Hub
    bInterfaceSubClass      0 
    bInterfaceProtocol      0 Full speed (or root) hub
    iInterface              0 
    Endpoint Descriptor:
      bLength                 7
      bDescriptorType         5
      bEndpointAddress     0x81  EP 1 IN
      bmAttributes            3
        Transfer Type            Interrupt
        Synch Type               None
        Usage Type               Data
      wMaxPacketSize     0x0001  1x 1 bytes
      bInterval              12

Oplysninger om PCI-enheder


PCI-enheder kan indeholde USB-porte, grafikkort, netværkskort osv. Lspci-værktøjet bruges til at generere oplysninger om alle PCI-controllere på dit system samt de enheder, der er forbundet med dem.

$ lspci

Her kun vist et lille afsnitet af outputet

00:00.0 Host bridge: Intel Corporation 4th Gen Core Processor DRAM Controller (rev 06)

00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor PCI Express x16 Controller (rev 06)

00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller (rev 06)

00:03.0 Audio device: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor HD Audio Controller (rev 06)

00:14.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI (rev 05)

00:16.0 Communication controller: Intel Corporation 8 Series/C220 Series Chipset Family MEI Controller #1 (rev 04)

00:1a.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 (rev 05)

00:1b.0 Audio device: Intel Corporation 8 Series/C220 Series Chipset High Definition Audio Controller (rev 05)

00:1c.0 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #1 (rev d5)

00:1c.2 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #3 (rev d5)

00:1c.4 PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #5 (rev d5)

00:1d.0 USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #1 (rev 05)

00:1f.0 ISA bridge: Intel Corporation C220 Series Chipset Family H81 Express LPC Controller (rev 05)

00:1f.2 SATA controller: Intel Corporation 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] (rev 05)

00:1f.3 SMBus: Intel Corporation 8 Series/C220 Series Chipset Family SMBus Controller (rev 05)

03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 0c)

04:00.0 USB controller: ASMedia Technology Inc. ASM1042A USB 3.0 Host Controller

Brug funktionen -v til at vise detaljerede oplysninger om hver tilsluttet enhed.

$ lspci -v

Her kun vist et lille afsnitet af outputet

00:00.0 Host bridge: Intel Corporation 4th Gen Core Processor DRAM Controller (rev 06)

Subsystem: ASUSTeK Computer Inc. 4th Gen Core Processor DRAM Controller
Flags: bus master, fast devsel, latency 0
Capabilities: <access denied>
Kernel driver in use: hsw_uncore

00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor PCI Express x16 Controller (rev 06) (prog-if 00 [Normal decode])

Flags: bus master, fast devsel, latency 0, IRQ 16
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: None
Memory behind bridge: None
Prefetchable memory behind bridge: None
Capabilities: <access denied>
Kernel driver in use: pcieport
Kernel modules: shpchp

00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller (rev 06) (prog-if 00 [VGA controller])

Subsystem: ASUSTeK Computer Inc. Xeon E3-1200 v3/4th Gen Core Processor Integrated Graphics Controller
Flags: bus master, fast devsel, latency 0, IRQ 34
Memory at f7800000 (64-bit, non-prefetchable) [size=4M]
Memory at e0000000 (64-bit, prefetchable) [size=256M]
I/O ports at f000 [size=64]
[virtual] Expansion ROM at 000c0000 [disabled] [size=128K]
Capabilities: <access denied>
Kernel driver in use: i915
Kernel modules: i915

Sådan vises SCSI-enheder


For at se alle dine scsi / sata-enheder skal du bruge kommandoen lsscsi (bl.a. SSD hardisk Hvis du ikke har lsscsi installeret, skal skal du installere det først inden du kan bruge komandoen.

$ lsscsi

[0:0:0:0] cd/dvd ASUS DRW-24F1ST a 1.00 /dev/sr0

[1:0:0:0] disk ATA Samsung SSD 840 8B0Q /dev/sda

[4:0:0:0] disk Seagate Expansion Desk 0911 /dev/sdb

[5:0:0:0] disk Seagate Expansion Desk 0911 /dev/sdc

Du kan finde nogle oplysninger om sata-enheder på dit system som følger ved hjælp af hdparm programmet. Hvis det ikke er instaleret, så installer det. I eksemplet nedenfor brugte jeg blokenheden / dev / sda2 som harddisken på mit system.

$ sudo hdparm -g /dev/sda2

/dev/sda2:

geometry = 60801/255/63, sectors = 960141312, start = 524288

Filsystem Information


For at vise oplysninger om filsystempartitioner, kan du bruge fdisk-kommandoen. Selv om fdisk-kommandoen vigtigste funktionalitet er at ændre filsystempartitioner, kan den også bruges til at se oplysninger om de forskellige partitioner på dit filsystem.

$ sudo fdisk -l

Disk /dev/sda: 465,8 GiB, 500107862016 byte, 976773168 sektorer

Enheder: sektorer af 1 * 512 = 512 byte

Sektorstørrelse (logisk/fysisk): 512 byte / 512 byte

I/O-størrelse (minimum/optimal): 512 byte / 512 byte

Disketikettype: dos Diskidentifikation: 0x8f3940d0

Enhed Opstart Start Slut Sektorer Størrelse Id Type

/dev/sda1 * 2048 524287 522240 255M 83 Linux

/dev/sda2 524288 960665599 960141312 457,9G 83 Linux

/dev/sda3 960665600 976773167 16107568 7,7G f W95 udvidet (LBA)

/dev/sda5 960667648 976773167 16105520 7,7G 82 Linux swap / Solaris

Disk /dev/sdb: 1,8 TiB, 2000398933504 byte, 3907029167 sektorer

Enheder: sektorer af 1 * 512 = 512 byte

Sektorstørrelse (logisk/fysisk): 512 byte / 4096 byte

I/O-størrelse (minimum/optimal): 4096 byte / 33553920 byte

Disketikettype: dos

Diskidentifikation: 0x5444d4ec Enhed Opstart Start Slut Sektorer Størrelse Id Type

/dev/sdb1 2048 3907028991 3907026944 1,8T 83 Linux

Disk /dev/sdc: 1,8 TiB, 2000398933504 byte, 3907029167 sektorer

Enheder: sektorer af 1 * 512 = 512 byte

Sektorstørrelse (logisk/fysisk): 512 byte / 4096 byte

I/O-størrelse (minimum/optimal): 4096 byte / 33553920 byte

Disketikettype: gpt

Diskidentifikation: 231FE121-424C-4E24-A816-6608A1CB2B09

Enhed Start Slut Sektorer Størrelse Type

/dev/sdc1 2048 3907028991 3907026944 1,8T Microsoft basisdata

Oplysninger om hardwarekomponenter


Du kan også bruge dmidecode-værktøjet, til at udvinde hardwareoplysninger ved at læse data fra DMI-tabellerne.

For at vise oplysninger om hukommelse, skal du være root.

$ sudo dmidecode -t memory

# dmidecode 3.1

Getting SMBIOS data from sysfs.

SMBIOS 2.7 present.

Handle 0x003B, DMI type 17, 34 bytes Memory Device

Array Handle: 0x003C
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: ChannelA-DIMM0
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MT/s
Manufacturer: Kingston
Serial Number: 12351717
Asset Tag: 9876543210
Part Number: KHX1600C10D3/8GX  
Rank: 2
Configured Clock Speed: 1600 MT/s

Handle 0x003C, DMI type 16, 23 bytes Physical Memory Array

Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 16 GB
Error Information Handle: Not Provided
Number Of Devices: 2

Handle 0x003E, DMI type 17, 34 bytes Memory Device

Array Handle: 0x003C
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: ChannelB-DIMM0
Bank Locator: BANK 2
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MT/s
Manufacturer: Kingston
Serial Number: 11352617
Asset Tag: 9876543210
Part Number: KHX1600C10D3/8GX  
Rank: 2
Configured Clock Speed: 1600 MT/s

Kommando for at få vist oplysninger om systemet.

$ sudo dmidecode -t system

# dmidecode 3.1

Getting SMBIOS data from sysfs.

SMBIOS 2.7 present.

Handle 0x0001, DMI type 1, 27 bytes System Information

Manufacturer: ASUS
Product Name: All Series
Version: System Version
Serial Number: System Serial Number
UUID: B0373AA2-D404-7872-7A22-E03F4982C8E2
Wake-up Type: Power Switch
SKU Number: All
Family: ASUS MB

Handle 0x001F, DMI type 12, 5 bytes System Configuration Options

Option 1: To Be Filled By O.E.M.

Handle 0x0021, DMI type 32, 20 bytes System Boot Information

Status: No errors detected

Vis oplysninger om BIOS, brug denne kommando.

$ sudo dmidecode -t bios

# dmidecode 3.1

Getting SMBIOS data from sysfs.

SMBIOS 2.7 present.

Handle 0x0000, DMI type 0, 24 bytes BIOS Information

Vendor: American Megatrends Inc.
Version: 0701
Release Date: 12/03/2013
Address: 0xF0000
Runtime Size: 64 kB
ROM Size: 8192 kB
Characteristics:
	PCI is supported
	APM is supported
	BIOS is upgradeable
	BIOS shadowing is allowed
	Boot from CD is supported
	Selectable boot is supported
	BIOS ROM is socketed
	EDD is supported
	5.25"/1.2 MB floppy services are supported (int 13h)
	3.5"/720 kB floppy services are supported (int 13h)
	3.5"/2.88 MB floppy services are supported (int 13h)
	Print screen service is supported (int 5h)
	8042 keyboard services are supported (int 9h)
	Serial services are supported (int 14h)
	Printer services are supported (int 17h)
	ACPI is supported
	USB legacy is supported
	BIOS boot specification is supported
	Targeted content distribution is supported
	UEFI is supported
BIOS Revision: 4.6

Handle 0x0052, DMI type 13, 22 bytes BIOS Language Information

Language Description Format: Long
Installable Languages: 8
	en|US|iso8859-1
	fr|FR|iso8859-1
	es|ES|iso8859-1
	de|DE|iso8859-1
	ru|RU|iso8859-5
	ko|KR|unicode
	ja|JP|unicode
	zh|CN|unicode
Currently Installed Language: en|US|iso8859-1

Udfør denne kommando for at vise oplysninger om processor.

$ sudo dmidecode -t processor

# dmidecode 3.1

Getting SMBIOS data from sysfs.

SMBIOS 2.7 present.

Handle 0x004C, DMI type 4, 42 bytes Processor Information

Socket Designation: SOCKET 1150
Type: Central Processor
Family: Other
Manufacturer: Intel
ID: C3 06 03 00 FF FB EB BF
Version: Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz
Voltage: 1.2 V
External Clock: 100 MHz
Max Speed: 3900 MHz
Current Speed: 3207 MHz
Status: Populated, Enabled
Upgrade: Socket BGA1155
L1 Cache Handle: 0x0041
L2 Cache Handle: 0x0042
L3 Cache Handle: 0x0043
Serial Number: Not Specified
Asset Tag: Fill By OEM
Part Number: Fill By OEM
Core Count: 4
Core Enabled: 4
Thread Count: 4
Characteristics:
64-bit capable

Cpuid komando - Viser x86 CPU


Kommandoen cpuid vise fuldstændig information om CPU'en (erne) indsamlet fra CPUID instruktionen, og viser også den nøjagtige model af x86 CPU'er fra disse oplysninger.

Sørg for at installere cpuid , før du bruger komandoen.

$ cpuid

CPU 0:

 vendor_id = "GenuineIntel"
 version information (1/eax):
    processor type  = primary processor (0)
    family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
    model           = 0xc (12)
    stepping id     = 0x3 (3)
    extended family = 0x0 (0)
    extended model  = 0x3 (3)
    (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
 miscellaneous (1/ebx):
    process local APIC physical ID = 0x0 (0)
    cpu count                      = 0x10 (16)
    CLFLUSH line size              = 0x8 (8)
    brand index                    = 0x0 (0)
 brand id = 0x00 (0): unknown
 feature information (1/edx):
    x87 FPU on chip                        = true
    virtual-8086 mode enhancement          = true
    debugging extensions                   = true
    page size extensions                   = true
    time stamp counter                     = true
    RDMSR and WRMSR support                = true
    physical address extensions            = true
    machine check exception                = true
    CMPXCHG8B inst.                        = true
    APIC on chip                           = true
    SYSENTER and SYSEXIT                   = true
    memory type range registers            = true
    PTE global bit                         = true
    machine check architecture             = true
    conditional move/compare instruction   = true
    page attribute table                   = true
    page size extension                    = true
    processor serial number                = false
    CLFLUSH instruction                    = true
    debug store                            = true
    thermal monitor and clock ctrl         = true
    MMX Technology                         = true
    FXSAVE/FXRSTOR                         = true
    SSE extensions                         = true
    SSE2 extensions                        = true
    self snoop                             = true
    hyper-threading / multi-core supported = true
    therm. monitor                         = true
    IA64                                   = false
    pending break event                    = true
 feature information (1/ecx):
    PNI/SSE3: Prescott New Instructions     = true
    PCLMULDQ instruction                    = true
    64-bit debug store                      = true
    MONITOR/MWAIT                           = true
    CPL-qualified debug store               = true
    VMX: virtual machine extensions         = true
    SMX: safer mode extensions              = true
    Enhanced Intel SpeedStep Technology     = true
    thermal monitor 2                       = true
    SSSE3 extensions                        = true
    context ID: adaptive or shared L1 data  = false
    FMA instruction                         = true
    CMPXCHG16B instruction                  = true
    xTPR disable                            = true
    perfmon and debug                       = true
    process context identifiers             = true
    direct cache access                     = false
    SSE4.1 extensions                       = true
    SSE4.2 extensions                       = true
    extended xAPIC support                  = true
    MOVBE instruction                       = true
    POPCNT instruction                      = true
    time stamp counter deadline             = true
    AES instruction                         = true
    XSAVE/XSTOR states                      = true
    OS-enabled XSAVE/XSTOR                  = true
    AVX: advanced vector extensions         = true
    F16C half-precision convert instruction = true
    RDRAND instruction                      = true
    hypervisor guest status                 = false
 cache and TLB information (2):
    0x63: data TLB: 1G pages, 4-way, 4 entries
    0x03: data TLB: 4K pages, 4-way, 64 entries
    0x76: instruction TLB: 2M/4M pages, fully, 8 entries
    0xff: cache data is in CPUID 4
    0xb6: instruction TLB: 4K, 8-way, 128 entries
    0xf0: 64 byte prefetching
    0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
 processor serial number: 0003-06C3-0000-0000-0000-0000
 deterministic cache parameters (4):
    --- cache 0 ---
    cache type                           = data cache (1)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 1 ---
    cache type                           = instruction cache (2)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 2 ---
    cache type                           = unified cache (3)
    cache level                          = 0x2 (2)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 511
    --- cache 3 ---
    cache type                           = unified cache (3)
    cache level                          = 0x3 (3)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0xf (15)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0xb (11)
    ways of associativity                = 0x6 (6)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = true
    complex cache indexing               = true
    number of sets - 1 (s)               = 8191
 MONITOR/MWAIT (5):
    smallest monitor-line size (bytes)       = 0x40 (64)
    largest monitor-line size (bytes)        = 0x40 (64)
    enum of Monitor-MWAIT exts supported     = true
    supports intrs as break-event for MWAIT  = true
    number of C0 sub C-states using MWAIT    = 0x0 (0)
    number of C1 sub C-states using MWAIT    = 0x2 (2)
    number of C2 sub C-states using MWAIT    = 0x1 (1)
    number of C3 sub C-states using MWAIT    = 0x2 (2)
    number of C4 sub C-states using MWAIT    = 0x4 (4)
    number of C5 sub C-states using MWAIT    = 0x0 (0)
    number of C6 sub C-states using MWAIT    = 0x0 (0)
    number of C7 sub C-states using MWAIT    = 0x0 (0)
 Thermal and Power Management Features (6):
    digital thermometer                     = true
    Intel Turbo Boost Technology            = true
    ARAT always running APIC timer          = true
    PLN power limit notification            = true
    ECMD extended clock modulation duty     = true
    PTM package thermal management          = true
    HWP base registers                      = false
    HWP notification                        = false
    HWP activity window                     = false
    HWP energy performance preference       = false
    HWP package level request               = false
    HDC base registers                      = false
    digital thermometer thresholds          = 0x2 (2)
    ACNT/MCNT supported performance measure = true
    ACNT2 available                         = false
    performance-energy bias capability      = true
 extended feature flags (7):
    FSGSBASE instructions                    = true
    IA32_TSC_ADJUST MSR supported            = true
    SGX: Software Guard Extensions supported = false
    BMI instruction                          = true
    HLE hardware lock elision                = false
    AVX2: advanced vector extensions 2       = true
    FDP_EXCPTN_ONLY                          = false
    SMEP supervisor mode exec protection     = true
    BMI2 instructions                        = true
    enhanced REP MOVSB/STOSB                 = true
    INVPCID instruction                      = true
    RTM: restricted transactional memory     = false
    QM: quality of service monitoring        = false
    deprecated FPU CS/DS                     = true
    intel memory protection extensions       = false
    PQE: platform quality of service enforce = false
    AVX512F: AVX-512 foundation instructions = false
    AVX512DQ: double & quadword instructions = false
    RDSEED instruction                       = false
    ADX instructions                         = false
    SMAP: supervisor mode access prevention  = false
    AVX512IFMA: fused multiply add           = false
    CLFLUSHOPT instruction                   = false
    CLWB instruction                         = false
    Intel processor trace                    = false
    AVX512PF: prefetch instructions          = false
    AVX512ER: exponent & reciprocal instrs   = false
    AVX512CD: conflict detection instrs      = false
    SHA instructions                         = false
    AVX512BW: byte & word instructions       = false
    AVX512VL: vector length                  = false
    PREFETCHWT1                              = false
    AVX512VBMI: vector byte manipulation     = false
    UMIP: user-mode instruction prevention   = false
    PKU protection keys for user-mode        = false
    OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
    BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
    RDPID: read processor D supported        = false
    SGX_LC: SGX launch config supported      = false
    AVX512_4VNNIW: neural network instrs     = false
    AVX512_4FMAPS: multiply acc single prec  = false
 Direct Cache Access Parameters (9):
    PLATFORM_DCA_CAP MSR bits = 0
 Architecture Performance Monitoring Features (0xa/eax):
    version ID                               = 0x3 (3)
    number of counters per logical processor = 0x8 (8)
    bit width of counter                     = 0x30 (48)
    length of EBX bit vector                 = 0x7 (7)
 Architecture Performance Monitoring Features (0xa/ebx):
    core cycle event not available           = false
    instruction retired event not available  = false
    reference cycles event not available     = false
    last-level cache ref event not available = false
    last-level cache miss event not avail    = false
    branch inst retired event not available  = false
    branch mispred retired event not avail   = false
 Architecture Performance Monitoring Features (0xa/edx):
    number of fixed counters    = 0x3 (3)
    bit width of fixed counters = 0x30 (48)
 x2APIC features / processor topology (0xb):
    --- level 0 (thread) ---
    bits to shift APIC ID to get next = 0x1 (1)
    logical processors at this level  = 0x1 (1)
    level number                      = 0x0 (0)
    level type                        = thread (1)
    extended APIC ID                  = 0
    --- level 1 (core) ---
    bits to shift APIC ID to get next = 0x4 (4)
    logical processors at this level  = 0x4 (4)
    level number                      = 0x1 (1)
    level type                        = core (2)
    extended APIC ID                  = 0
 XSAVE features (0xd/0):
    XCR0 lower 32 bits valid bit field mask = 0x00000007
    XCR0 upper 32 bits valid bit field mask = 0x00000000
       XCR0 supported: x87 state            = true
       XCR0 supported: SSE state            = true
       XCR0 supported: AVX state            = true
       XCR0 supported: MPX BNDREGS          = false
       XCR0 supported: MPX BNDCSR           = false
       XCR0 supported: AVX-512 opmask       = false
       XCR0 supported: AVX-512 ZMM_Hi256    = false
       XCR0 supported: AVX-512 Hi16_ZMM     = false
       IA32_XSS supported: PT state         = false
       XCR0 supported: PKRU state           = false
    bytes required by fields in XCR0        = 0x00000340 (832)
    bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
 XSAVE features (0xd/1):
    XSAVEOPT instruction                        = true
    XSAVEC instruction                          = false
    XGETBV instruction                          = false
    XSAVES/XRSTORS instructions                 = false
    SAVE area size in bytes                     = 0x00000000 (0)
    IA32_XSS lower 32 bits valid bit field mask = 0x00000000
    IA32_XSS upper 32 bits valid bit field mask = 0x00000000
 AVX/YMM features (0xd/2):
    AVX/YMM save state byte size             = 0x00000100 (256)
    AVX/YMM save state byte offset           = 0x00000240 (576)
    supported in IA32_XSS or XCR0            = XCR0 (user state)
    64-byte alignment in compacted XSAVE     = false
 extended feature flags (0x80000001/edx):
    SYSCALL and SYSRET instructions        = true
    execution disable                      = true
    1-GB large page support                = true
    RDTSCP                                 = true
    64-bit extensions technology available = true
 Intel feature flags (0x80000001/ecx):
    LAHF/SAHF supported in 64-bit mode     = true
    LZCNT advanced bit manipulation        = true
    3DNow! PREFETCH/PREFETCHW instructions = false
 brand = "Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz"
 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 data cache information (0x80000005/ecx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L1 instruction cache information (0x80000005/edx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 unified cache information (0x80000006/ecx):
    line size (bytes) = 0x40 (64)
    lines per tag     = 0x0 (0)
    associativity     = 8-way (6)
    size (KB)         = 0x100 (256)
 L3 cache information (0x80000006/edx):
    line size (bytes)     = 0x0 (0)
    lines per tag         = 0x0 (0)
    associativity         = L2 off (0)
    size (in 512KB units) = 0x0 (0)
 Advanced Power Management Features (0x80000007/edx):
    temperature sensing diode      = false
    frequency ID (FID) control     = false
    voltage ID (VID) control       = false
    thermal trip (TTP)             = false
    thermal monitor (TM)           = false
    software thermal control (STC) = false
    100 MHz multiplier control     = false
    hardware P-State control       = false
    TscInvariant                   = true
 Physical Address and Linear Address Size (0x80000008/eax):
    maximum physical address bits         = 0x27 (39)
    maximum linear (virtual) address bits = 0x30 (48)
    maximum guest physical address bits   = 0x0 (0)
 Logical CPU cores (0x80000008/ecx):
    number of CPU cores - 1 = 0x0 (0)
    ApicIdCoreIdSize        = 0x0 (0)
 (multi-processing synth): multi-core (c=4)
 (multi-processing method): Intel leaf 0xb
 (APIC widths synth): CORE_width=4 SMT_width=1
 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
 (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm

CPU 1:

 vendor_id = "GenuineIntel"
 version information (1/eax):
    processor type  = primary processor (0)
    family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
    model           = 0xc (12)
    stepping id     = 0x3 (3)
    extended family = 0x0 (0)
    extended model  = 0x3 (3)
    (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
 miscellaneous (1/ebx):
    process local APIC physical ID = 0x2 (2)
    cpu count                      = 0x10 (16)
    CLFLUSH line size              = 0x8 (8)
    brand index                    = 0x0 (0)
 brand id = 0x00 (0): unknown
 feature information (1/edx):
    x87 FPU on chip                        = true
    virtual-8086 mode enhancement          = true
    debugging extensions                   = true
    page size extensions                   = true
    time stamp counter                     = true
    RDMSR and WRMSR support                = true
    physical address extensions            = true
    machine check exception                = true
    CMPXCHG8B inst.                        = true
    APIC on chip                           = true
    SYSENTER and SYSEXIT                   = true
    memory type range registers            = true
    PTE global bit                         = true
    machine check architecture             = true
    conditional move/compare instruction   = true
    page attribute table                   = true
    page size extension                    = true
    processor serial number                = false
    CLFLUSH instruction                    = true
    debug store                            = true
    thermal monitor and clock ctrl         = true
    MMX Technology                         = true
    FXSAVE/FXRSTOR                         = true
    SSE extensions                         = true
    SSE2 extensions                        = true
    self snoop                             = true
    hyper-threading / multi-core supported = true
    therm. monitor                         = true
    IA64                                   = false
    pending break event                    = true
 feature information (1/ecx):
    PNI/SSE3: Prescott New Instructions     = true
    PCLMULDQ instruction                    = true
    64-bit debug store                      = true
    MONITOR/MWAIT                           = true
    CPL-qualified debug store               = true
    VMX: virtual machine extensions         = true
    SMX: safer mode extensions              = true
    Enhanced Intel SpeedStep Technology     = true
    thermal monitor 2                       = true
    SSSE3 extensions                        = true
    context ID: adaptive or shared L1 data  = false
    FMA instruction                         = true
    CMPXCHG16B instruction                  = true
    xTPR disable                            = true
    perfmon and debug                       = true
    process context identifiers             = true
    direct cache access                     = false
    SSE4.1 extensions                       = true
    SSE4.2 extensions                       = true
    extended xAPIC support                  = true
    MOVBE instruction                       = true
    POPCNT instruction                      = true
    time stamp counter deadline             = true
    AES instruction                         = true
    XSAVE/XSTOR states                      = true
    OS-enabled XSAVE/XSTOR                  = true
    AVX: advanced vector extensions         = true
    F16C half-precision convert instruction = true
    RDRAND instruction                      = true
    hypervisor guest status                 = false
 cache and TLB information (2):
    0x63: data TLB: 1G pages, 4-way, 4 entries
    0x03: data TLB: 4K pages, 4-way, 64 entries
    0x76: instruction TLB: 2M/4M pages, fully, 8 entries
    0xff: cache data is in CPUID 4
    0xb6: instruction TLB: 4K, 8-way, 128 entries
    0xf0: 64 byte prefetching
    0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
 processor serial number: 0003-06C3-0000-0000-0000-0000
 deterministic cache parameters (4):
    --- cache 0 ---
    cache type                           = data cache (1)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 1 ---
    cache type                           = instruction cache (2)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 2 ---
    cache type                           = unified cache (3)
    cache level                          = 0x2 (2)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 511
    --- cache 3 ---
    cache type                           = unified cache (3)
    cache level                          = 0x3 (3)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0xf (15)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0xb (11)
    ways of associativity                = 0x6 (6)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = true
    complex cache indexing               = true
    number of sets - 1 (s)               = 8191
 MONITOR/MWAIT (5):
    smallest monitor-line size (bytes)       = 0x40 (64)
    largest monitor-line size (bytes)        = 0x40 (64)
    enum of Monitor-MWAIT exts supported     = true
    supports intrs as break-event for MWAIT  = true
    number of C0 sub C-states using MWAIT    = 0x0 (0)
    number of C1 sub C-states using MWAIT    = 0x2 (2)
    number of C2 sub C-states using MWAIT    = 0x1 (1)
    number of C3 sub C-states using MWAIT    = 0x2 (2)
    number of C4 sub C-states using MWAIT    = 0x4 (4)
    number of C5 sub C-states using MWAIT    = 0x0 (0)
    number of C6 sub C-states using MWAIT    = 0x0 (0)
    number of C7 sub C-states using MWAIT    = 0x0 (0)
 Thermal and Power Management Features (6):
    digital thermometer                     = true
    Intel Turbo Boost Technology            = true
    ARAT always running APIC timer          = true
    PLN power limit notification            = true
    ECMD extended clock modulation duty     = true
    PTM package thermal management          = true
    HWP base registers                      = false
    HWP notification                        = false
    HWP activity window                     = false
    HWP energy performance preference       = false
    HWP package level request               = false
    HDC base registers                      = false
    digital thermometer thresholds          = 0x2 (2)
    ACNT/MCNT supported performance measure = true
    ACNT2 available                         = false
    performance-energy bias capability      = true
 extended feature flags (7):
    FSGSBASE instructions                    = true
    IA32_TSC_ADJUST MSR supported            = true
    SGX: Software Guard Extensions supported = false
    BMI instruction                          = true
    HLE hardware lock elision                = false
    AVX2: advanced vector extensions 2       = true
    FDP_EXCPTN_ONLY                          = false
    SMEP supervisor mode exec protection     = true
    BMI2 instructions                        = true
    enhanced REP MOVSB/STOSB                 = true
    INVPCID instruction                      = true
    RTM: restricted transactional memory     = false
    QM: quality of service monitoring        = false
    deprecated FPU CS/DS                     = true
    intel memory protection extensions       = false
    PQE: platform quality of service enforce = false
    AVX512F: AVX-512 foundation instructions = false
    AVX512DQ: double & quadword instructions = false
    RDSEED instruction                       = false
    ADX instructions                         = false
    SMAP: supervisor mode access prevention  = false
    AVX512IFMA: fused multiply add           = false
    CLFLUSHOPT instruction                   = false
    CLWB instruction                         = false
    Intel processor trace                    = false
    AVX512PF: prefetch instructions          = false
    AVX512ER: exponent & reciprocal instrs   = false
    AVX512CD: conflict detection instrs      = false
    SHA instructions                         = false
    AVX512BW: byte & word instructions       = false
    AVX512VL: vector length                  = false
    PREFETCHWT1                              = false
    AVX512VBMI: vector byte manipulation     = false
    UMIP: user-mode instruction prevention   = false
    PKU protection keys for user-mode        = false
    OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
    BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
    RDPID: read processor D supported        = false
    SGX_LC: SGX launch config supported      = false
    AVX512_4VNNIW: neural network instrs     = false
    AVX512_4FMAPS: multiply acc single prec  = false
 Direct Cache Access Parameters (9):
    PLATFORM_DCA_CAP MSR bits = 0
 Architecture Performance Monitoring Features (0xa/eax):
    version ID                               = 0x3 (3)
    number of counters per logical processor = 0x8 (8)
    bit width of counter                     = 0x30 (48)
    length of EBX bit vector                 = 0x7 (7)
 Architecture Performance Monitoring Features (0xa/ebx):
    core cycle event not available           = false
    instruction retired event not available  = false
    reference cycles event not available     = false
    last-level cache ref event not available = false
    last-level cache miss event not avail    = false
    branch inst retired event not available  = false
    branch mispred retired event not avail   = false
 Architecture Performance Monitoring Features (0xa/edx):
    number of fixed counters    = 0x3 (3)
    bit width of fixed counters = 0x30 (48)
 x2APIC features / processor topology (0xb):
    --- level 0 (thread) ---
    bits to shift APIC ID to get next = 0x1 (1)
    logical processors at this level  = 0x1 (1)
    level number                      = 0x0 (0)
    level type                        = thread (1)
    extended APIC ID                  = 2
    --- level 1 (core) ---
    bits to shift APIC ID to get next = 0x4 (4)
    logical processors at this level  = 0x4 (4)
    level number                      = 0x1 (1)
    level type                        = core (2)
    extended APIC ID                  = 2
 XSAVE features (0xd/0):
    XCR0 lower 32 bits valid bit field mask = 0x00000007
    XCR0 upper 32 bits valid bit field mask = 0x00000000
       XCR0 supported: x87 state            = true
       XCR0 supported: SSE state            = true
       XCR0 supported: AVX state            = true
       XCR0 supported: MPX BNDREGS          = false
       XCR0 supported: MPX BNDCSR           = false
       XCR0 supported: AVX-512 opmask       = false
       XCR0 supported: AVX-512 ZMM_Hi256    = false
       XCR0 supported: AVX-512 Hi16_ZMM     = false
       IA32_XSS supported: PT state         = false
       XCR0 supported: PKRU state           = false
    bytes required by fields in XCR0        = 0x00000340 (832)
    bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
 XSAVE features (0xd/1):
    XSAVEOPT instruction                        = true
    XSAVEC instruction                          = false
    XGETBV instruction                          = false
    XSAVES/XRSTORS instructions                 = false
    SAVE area size in bytes                     = 0x00000000 (0)
    IA32_XSS lower 32 bits valid bit field mask = 0x00000000
    IA32_XSS upper 32 bits valid bit field mask = 0x00000000
 AVX/YMM features (0xd/2):
    AVX/YMM save state byte size             = 0x00000100 (256)
    AVX/YMM save state byte offset           = 0x00000240 (576)
    supported in IA32_XSS or XCR0            = XCR0 (user state)
    64-byte alignment in compacted XSAVE     = false
 extended feature flags (0x80000001/edx):
    SYSCALL and SYSRET instructions        = true
    execution disable                      = true
    1-GB large page support                = true
    RDTSCP                                 = true
    64-bit extensions technology available = true
 Intel feature flags (0x80000001/ecx):
    LAHF/SAHF supported in 64-bit mode     = true
    LZCNT advanced bit manipulation        = true
    3DNow! PREFETCH/PREFETCHW instructions = false
 brand = "Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz"
 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 data cache information (0x80000005/ecx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L1 instruction cache information (0x80000005/edx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 unified cache information (0x80000006/ecx):
    line size (bytes) = 0x40 (64)
    lines per tag     = 0x0 (0)
    associativity     = 8-way (6)
    size (KB)         = 0x100 (256)
 L3 cache information (0x80000006/edx):
    line size (bytes)     = 0x0 (0)
    lines per tag         = 0x0 (0)
    associativity         = L2 off (0)
    size (in 512KB units) = 0x0 (0)
 Advanced Power Management Features (0x80000007/edx):
    temperature sensing diode      = false
    frequency ID (FID) control     = false
    voltage ID (VID) control       = false
    thermal trip (TTP)             = false
    thermal monitor (TM)           = false
    software thermal control (STC) = false
    100 MHz multiplier control     = false
    hardware P-State control       = false
    TscInvariant                   = true
 Physical Address and Linear Address Size (0x80000008/eax):
    maximum physical address bits         = 0x27 (39)
    maximum linear (virtual) address bits = 0x30 (48)
    maximum guest physical address bits   = 0x0 (0)
 Logical CPU cores (0x80000008/ecx):
    number of CPU cores - 1 = 0x0 (0)
    ApicIdCoreIdSize        = 0x0 (0)
 (multi-processing synth): multi-core (c=4)
 (multi-processing method): Intel leaf 0xb
 (APIC widths synth): CORE_width=4 SMT_width=1
 (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
 (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm

CPU 2:

 vendor_id = "GenuineIntel"
 version information (1/eax):
    processor type  = primary processor (0)
    family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
    model           = 0xc (12)
    stepping id     = 0x3 (3)
    extended family = 0x0 (0)
    extended model  = 0x3 (3)
    (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
 miscellaneous (1/ebx):
    process local APIC physical ID = 0x4 (4)
    cpu count                      = 0x10 (16)
    CLFLUSH line size              = 0x8 (8)
    brand index                    = 0x0 (0)
 brand id = 0x00 (0): unknown
 feature information (1/edx):
    x87 FPU on chip                        = true
    virtual-8086 mode enhancement          = true
    debugging extensions                   = true
    page size extensions                   = true
    time stamp counter                     = true
    RDMSR and WRMSR support                = true
    physical address extensions            = true
    machine check exception                = true
    CMPXCHG8B inst.                        = true
    APIC on chip                           = true
    SYSENTER and SYSEXIT                   = true
    memory type range registers            = true
    PTE global bit                         = true
    machine check architecture             = true
    conditional move/compare instruction   = true
    page attribute table                   = true
    page size extension                    = true
    processor serial number                = false
    CLFLUSH instruction                    = true
    debug store                            = true
    thermal monitor and clock ctrl         = true
    MMX Technology                         = true
    FXSAVE/FXRSTOR                         = true
    SSE extensions                         = true
    SSE2 extensions                        = true
    self snoop                             = true
    hyper-threading / multi-core supported = true
    therm. monitor                         = true
    IA64                                   = false
    pending break event                    = true
 feature information (1/ecx):
    PNI/SSE3: Prescott New Instructions     = true
    PCLMULDQ instruction                    = true
    64-bit debug store                      = true
    MONITOR/MWAIT                           = true
    CPL-qualified debug store               = true
    VMX: virtual machine extensions         = true
    SMX: safer mode extensions              = true
    Enhanced Intel SpeedStep Technology     = true
    thermal monitor 2                       = true
    SSSE3 extensions                        = true
    context ID: adaptive or shared L1 data  = false
    FMA instruction                         = true
    CMPXCHG16B instruction                  = true
    xTPR disable                            = true
    perfmon and debug                       = true
    process context identifiers             = true
    direct cache access                     = false
    SSE4.1 extensions                       = true
    SSE4.2 extensions                       = true
    extended xAPIC support                  = true
    MOVBE instruction                       = true
    POPCNT instruction                      = true
    time stamp counter deadline             = true
    AES instruction                         = true
    XSAVE/XSTOR states                      = true
    OS-enabled XSAVE/XSTOR                  = true
    AVX: advanced vector extensions         = true
    F16C half-precision convert instruction = true
    RDRAND instruction                      = true
    hypervisor guest status                 = false
 cache and TLB information (2):
    0x63: data TLB: 1G pages, 4-way, 4 entries
    0x03: data TLB: 4K pages, 4-way, 64 entries
    0x76: instruction TLB: 2M/4M pages, fully, 8 entries
    0xff: cache data is in CPUID 4
    0xb6: instruction TLB: 4K, 8-way, 128 entries
    0xf0: 64 byte prefetching
    0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
 processor serial number: 0003-06C3-0000-0000-0000-0000
 deterministic cache parameters (4):
    --- cache 0 ---
    cache type                           = data cache (1)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 1 ---
    cache type                           = instruction cache (2)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 2 ---
    cache type                           = unified cache (3)
    cache level                          = 0x2 (2)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 511
    --- cache 3 ---
    cache type                           = unified cache (3)
    cache level                          = 0x3 (3)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0xf (15)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0xb (11)
    ways of associativity                = 0x6 (6)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = true
    complex cache indexing               = true
    number of sets - 1 (s)               = 8191
 MONITOR/MWAIT (5):
    smallest monitor-line size (bytes)       = 0x40 (64)
    largest monitor-line size (bytes)        = 0x40 (64)
    enum of Monitor-MWAIT exts supported     = true
    supports intrs as break-event for MWAIT  = true
    number of C0 sub C-states using MWAIT    = 0x0 (0)
    number of C1 sub C-states using MWAIT    = 0x2 (2)
    number of C2 sub C-states using MWAIT    = 0x1 (1)
    number of C3 sub C-states using MWAIT    = 0x2 (2)
    number of C4 sub C-states using MWAIT    = 0x4 (4)
    number of C5 sub C-states using MWAIT    = 0x0 (0)
    number of C6 sub C-states using MWAIT    = 0x0 (0)
    number of C7 sub C-states using MWAIT    = 0x0 (0)
 Thermal and Power Management Features (6):
    digital thermometer                     = true
    Intel Turbo Boost Technology            = true
    ARAT always running APIC timer          = true
    PLN power limit notification            = true
    ECMD extended clock modulation duty     = true
    PTM package thermal management          = true
    HWP base registers                      = false
    HWP notification                        = false
    HWP activity window                     = false
    HWP energy performance preference       = false
    HWP package level request               = false
    HDC base registers                      = false
    digital thermometer thresholds          = 0x2 (2)
    ACNT/MCNT supported performance measure = true
    ACNT2 available                         = false
    performance-energy bias capability      = true
 extended feature flags (7):
    FSGSBASE instructions                    = true
    IA32_TSC_ADJUST MSR supported            = true
    SGX: Software Guard Extensions supported = false
    BMI instruction                          = true
    HLE hardware lock elision                = false
    AVX2: advanced vector extensions 2       = true
    FDP_EXCPTN_ONLY                          = false
    SMEP supervisor mode exec protection     = true
    BMI2 instructions                        = true
    enhanced REP MOVSB/STOSB                 = true
    INVPCID instruction                      = true
    RTM: restricted transactional memory     = false
    QM: quality of service monitoring        = false
    deprecated FPU CS/DS                     = true
    intel memory protection extensions       = false
    PQE: platform quality of service enforce = false
    AVX512F: AVX-512 foundation instructions = false
    AVX512DQ: double & quadword instructions = false
    RDSEED instruction                       = false
    ADX instructions                         = false
    SMAP: supervisor mode access prevention  = false
    AVX512IFMA: fused multiply add           = false
    CLFLUSHOPT instruction                   = false
    CLWB instruction                         = false
    Intel processor trace                    = false
    AVX512PF: prefetch instructions          = false
    AVX512ER: exponent & reciprocal instrs   = false
    AVX512CD: conflict detection instrs      = false
    SHA instructions                         = false
    AVX512BW: byte & word instructions       = false
    AVX512VL: vector length                  = false
    PREFETCHWT1                              = false
    AVX512VBMI: vector byte manipulation     = false
    UMIP: user-mode instruction prevention   = false
    PKU protection keys for user-mode        = false
    OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
    BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
    RDPID: read processor D supported        = false
    SGX_LC: SGX launch config supported      = false
    AVX512_4VNNIW: neural network instrs     = false
    AVX512_4FMAPS: multiply acc single prec  = false
 Direct Cache Access Parameters (9):
    PLATFORM_DCA_CAP MSR bits = 0
 Architecture Performance Monitoring Features (0xa/eax):
    version ID                               = 0x3 (3)
    number of counters per logical processor = 0x8 (8)
    bit width of counter                     = 0x30 (48)
    length of EBX bit vector                 = 0x7 (7)
 Architecture Performance Monitoring Features (0xa/ebx):
    core cycle event not available           = false
    instruction retired event not available  = false
    reference cycles event not available     = false
    last-level cache ref event not available = false
    last-level cache miss event not avail    = false
    branch inst retired event not available  = false
    branch mispred retired event not avail   = false
 Architecture Performance Monitoring Features (0xa/edx):
    number of fixed counters    = 0x3 (3)
    bit width of fixed counters = 0x30 (48)
 x2APIC features / processor topology (0xb):
    --- level 0 (thread) ---
    bits to shift APIC ID to get next = 0x1 (1)
    logical processors at this level  = 0x1 (1)
    level number                      = 0x0 (0)
    level type                        = thread (1)
    extended APIC ID                  = 4
    --- level 1 (core) ---
    bits to shift APIC ID to get next = 0x4 (4)
    logical processors at this level  = 0x4 (4)
    level number                      = 0x1 (1)
    level type                        = core (2)
    extended APIC ID                  = 4
 XSAVE features (0xd/0):
    XCR0 lower 32 bits valid bit field mask = 0x00000007
    XCR0 upper 32 bits valid bit field mask = 0x00000000
       XCR0 supported: x87 state            = true
       XCR0 supported: SSE state            = true
       XCR0 supported: AVX state            = true
       XCR0 supported: MPX BNDREGS          = false
       XCR0 supported: MPX BNDCSR           = false
       XCR0 supported: AVX-512 opmask       = false
       XCR0 supported: AVX-512 ZMM_Hi256    = false
       XCR0 supported: AVX-512 Hi16_ZMM     = false
       IA32_XSS supported: PT state         = false
       XCR0 supported: PKRU state           = false
    bytes required by fields in XCR0        = 0x00000340 (832)
    bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
 XSAVE features (0xd/1):
    XSAVEOPT instruction                        = true
    XSAVEC instruction                          = false
    XGETBV instruction                          = false
    XSAVES/XRSTORS instructions                 = false
    SAVE area size in bytes                     = 0x00000000 (0)
    IA32_XSS lower 32 bits valid bit field mask = 0x00000000
    IA32_XSS upper 32 bits valid bit field mask = 0x00000000
 AVX/YMM features (0xd/2):
    AVX/YMM save state byte size             = 0x00000100 (256)
    AVX/YMM save state byte offset           = 0x00000240 (576)
    supported in IA32_XSS or XCR0            = XCR0 (user state)
    64-byte alignment in compacted XSAVE     = false
 extended feature flags (0x80000001/edx):
    SYSCALL and SYSRET instructions        = true
    execution disable                      = true
    1-GB large page support                = true
    RDTSCP                                 = true
    64-bit extensions technology available = true
 Intel feature flags (0x80000001/ecx):
    LAHF/SAHF supported in 64-bit mode     = true
    LZCNT advanced bit manipulation        = true
    3DNow! PREFETCH/PREFETCHW instructions = false
 brand = "Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz"
 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 data cache information (0x80000005/ecx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L1 instruction cache information (0x80000005/edx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 unified cache information (0x80000006/ecx):
    line size (bytes) = 0x40 (64)
    lines per tag     = 0x0 (0)
    associativity     = 8-way (6)
    size (KB)         = 0x100 (256)
 L3 cache information (0x80000006/edx):
    line size (bytes)     = 0x0 (0)
    lines per tag         = 0x0 (0)
    associativity         = L2 off (0)
    size (in 512KB units) = 0x0 (0)
 Advanced Power Management Features (0x80000007/edx):
    temperature sensing diode      = false
    frequency ID (FID) control     = false
    voltage ID (VID) control       = false
    thermal trip (TTP)             = false
    thermal monitor (TM)           = false
    software thermal control (STC) = false
    100 MHz multiplier control     = false
    hardware P-State control       = false
    TscInvariant                   = true
 Physical Address and Linear Address Size (0x80000008/eax):
    maximum physical address bits         = 0x27 (39)
    maximum linear (virtual) address bits = 0x30 (48)
    maximum guest physical address bits   = 0x0 (0)
 Logical CPU cores (0x80000008/ecx):
    number of CPU cores - 1 = 0x0 (0)
    ApicIdCoreIdSize        = 0x0 (0)
 (multi-processing synth): multi-core (c=4)
 (multi-processing method): Intel leaf 0xb
 (APIC widths synth): CORE_width=4 SMT_width=1
 (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
 (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm

CPU 3:

 vendor_id = "GenuineIntel"
 version information (1/eax):
    processor type  = primary processor (0)
    family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
    model           = 0xc (12)
    stepping id     = 0x3 (3)
    extended family = 0x0 (0)
    extended model  = 0x3 (3)
    (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
 miscellaneous (1/ebx):
    process local APIC physical ID = 0x6 (6)
    cpu count                      = 0x10 (16)
    CLFLUSH line size              = 0x8 (8)
    brand index                    = 0x0 (0)
 brand id = 0x00 (0): unknown
 feature information (1/edx):
    x87 FPU on chip                        = true
    virtual-8086 mode enhancement          = true
    debugging extensions                   = true
    page size extensions                   = true
    time stamp counter                     = true
    RDMSR and WRMSR support                = true
    physical address extensions            = true
    machine check exception                = true
    CMPXCHG8B inst.                        = true
    APIC on chip                           = true
    SYSENTER and SYSEXIT                   = true
    memory type range registers            = true
    PTE global bit                         = true
    machine check architecture             = true
    conditional move/compare instruction   = true
    page attribute table                   = true
    page size extension                    = true
    processor serial number                = false
    CLFLUSH instruction                    = true
    debug store                            = true
    thermal monitor and clock ctrl         = true
    MMX Technology                         = true
    FXSAVE/FXRSTOR                         = true
    SSE extensions                         = true
    SSE2 extensions                        = true
    self snoop                             = true
    hyper-threading / multi-core supported = true
    therm. monitor                         = true
    IA64                                   = false
    pending break event                    = true
 feature information (1/ecx):
    PNI/SSE3: Prescott New Instructions     = true
    PCLMULDQ instruction                    = true
    64-bit debug store                      = true
    MONITOR/MWAIT                           = true
    CPL-qualified debug store               = true
    VMX: virtual machine extensions         = true
    SMX: safer mode extensions              = true
    Enhanced Intel SpeedStep Technology     = true
    thermal monitor 2                       = true
    SSSE3 extensions                        = true
    context ID: adaptive or shared L1 data  = false
    FMA instruction                         = true
    CMPXCHG16B instruction                  = true
    xTPR disable                            = true
    perfmon and debug                       = true
    process context identifiers             = true
    direct cache access                     = false
    SSE4.1 extensions                       = true
    SSE4.2 extensions                       = true
    extended xAPIC support                  = true
    MOVBE instruction                       = true
    POPCNT instruction                      = true
    time stamp counter deadline             = true
    AES instruction                         = true
    XSAVE/XSTOR states                      = true
    OS-enabled XSAVE/XSTOR                  = true
    AVX: advanced vector extensions         = true
    F16C half-precision convert instruction = true
    RDRAND instruction                      = true
    hypervisor guest status                 = false
 cache and TLB information (2):
    0x63: data TLB: 1G pages, 4-way, 4 entries
    0x03: data TLB: 4K pages, 4-way, 64 entries
    0x76: instruction TLB: 2M/4M pages, fully, 8 entries
    0xff: cache data is in CPUID 4
    0xb6: instruction TLB: 4K, 8-way, 128 entries
    0xf0: 64 byte prefetching
    0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
 processor serial number: 0003-06C3-0000-0000-0000-0000
 deterministic cache parameters (4):
    --- cache 0 ---
    cache type                           = data cache (1)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 1 ---
    cache type                           = instruction cache (2)
    cache level                          = 0x1 (1)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 63
    --- cache 2 ---
    cache type                           = unified cache (3)
    cache level                          = 0x2 (2)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0x1 (1)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0x7 (7)
    ways of associativity                = 0x0 (0)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = false
    complex cache indexing               = false
    number of sets - 1 (s)               = 511
    --- cache 3 ---
    cache type                           = unified cache (3)
    cache level                          = 0x3 (3)
    self-initializing cache level        = true
    fully associative cache              = false
    extra threads sharing this cache     = 0xf (15)
    extra processor cores on this die    = 0x7 (7)
    system coherency line size           = 0x3f (63)
    physical line partitions             = 0x0 (0)
    ways of associativity                = 0xb (11)
    ways of associativity                = 0x6 (6)
    WBINVD/INVD behavior on lower caches = false
    inclusive to lower caches            = true
    complex cache indexing               = true
    number of sets - 1 (s)               = 8191
 MONITOR/MWAIT (5):
    smallest monitor-line size (bytes)       = 0x40 (64)
    largest monitor-line size (bytes)        = 0x40 (64)
    enum of Monitor-MWAIT exts supported     = true
    supports intrs as break-event for MWAIT  = true
    number of C0 sub C-states using MWAIT    = 0x0 (0)
    number of C1 sub C-states using MWAIT    = 0x2 (2)
    number of C2 sub C-states using MWAIT    = 0x1 (1)
    number of C3 sub C-states using MWAIT    = 0x2 (2)
    number of C4 sub C-states using MWAIT    = 0x4 (4)
    number of C5 sub C-states using MWAIT    = 0x0 (0)
    number of C6 sub C-states using MWAIT    = 0x0 (0)
    number of C7 sub C-states using MWAIT    = 0x0 (0)
 Thermal and Power Management Features (6):
    digital thermometer                     = true
    Intel Turbo Boost Technology            = true
    ARAT always running APIC timer          = true
    PLN power limit notification            = true
    ECMD extended clock modulation duty     = true
    PTM package thermal management          = true
    HWP base registers                      = false
    HWP notification                        = false
    HWP activity window                     = false
    HWP energy performance preference       = false
    HWP package level request               = false
    HDC base registers                      = false
    digital thermometer thresholds          = 0x2 (2)
    ACNT/MCNT supported performance measure = true
    ACNT2 available                         = false
    performance-energy bias capability      = true
 extended feature flags (7):
    FSGSBASE instructions                    = true
    IA32_TSC_ADJUST MSR supported            = true
    SGX: Software Guard Extensions supported = false
    BMI instruction                          = true
    HLE hardware lock elision                = false
    AVX2: advanced vector extensions 2       = true
    FDP_EXCPTN_ONLY                          = false
    SMEP supervisor mode exec protection     = true
    BMI2 instructions                        = true
    enhanced REP MOVSB/STOSB                 = true
    INVPCID instruction                      = true
    RTM: restricted transactional memory     = false
    QM: quality of service monitoring        = false
    deprecated FPU CS/DS                     = true
    intel memory protection extensions       = false
    PQE: platform quality of service enforce = false
    AVX512F: AVX-512 foundation instructions = false
    AVX512DQ: double & quadword instructions = false
    RDSEED instruction                       = false
    ADX instructions                         = false
    SMAP: supervisor mode access prevention  = false
    AVX512IFMA: fused multiply add           = false
    CLFLUSHOPT instruction                   = false
    CLWB instruction                         = false
    Intel processor trace                    = false
    AVX512PF: prefetch instructions          = false
    AVX512ER: exponent & reciprocal instrs   = false
    AVX512CD: conflict detection instrs      = false
    SHA instructions                         = false
    AVX512BW: byte & word instructions       = false
    AVX512VL: vector length                  = false
    PREFETCHWT1                              = false
    AVX512VBMI: vector byte manipulation     = false
    UMIP: user-mode instruction prevention   = false
    PKU protection keys for user-mode        = false
    OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
    BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
    RDPID: read processor D supported        = false
    SGX_LC: SGX launch config supported      = false
    AVX512_4VNNIW: neural network instrs     = false
    AVX512_4FMAPS: multiply acc single prec  = false
 Direct Cache Access Parameters (9):
    PLATFORM_DCA_CAP MSR bits = 0
 Architecture Performance Monitoring Features (0xa/eax):
    version ID                               = 0x3 (3)
    number of counters per logical processor = 0x8 (8)
    bit width of counter                     = 0x30 (48)
    length of EBX bit vector                 = 0x7 (7)
 Architecture Performance Monitoring Features (0xa/ebx):
    core cycle event not available           = false
    instruction retired event not available  = false
    reference cycles event not available     = false
    last-level cache ref event not available = false
    last-level cache miss event not avail    = false
    branch inst retired event not available  = false
    branch mispred retired event not avail   = false
 Architecture Performance Monitoring Features (0xa/edx):
    number of fixed counters    = 0x3 (3)
    bit width of fixed counters = 0x30 (48)
 x2APIC features / processor topology (0xb):
    --- level 0 (thread) ---
    bits to shift APIC ID to get next = 0x1 (1)
    logical processors at this level  = 0x1 (1)
    level number                      = 0x0 (0)
    level type                        = thread (1)
    extended APIC ID                  = 6
    --- level 1 (core) ---
    bits to shift APIC ID to get next = 0x4 (4)
    logical processors at this level  = 0x4 (4)
    level number                      = 0x1 (1)
    level type                        = core (2)
    extended APIC ID                  = 6
 XSAVE features (0xd/0):
    XCR0 lower 32 bits valid bit field mask = 0x00000007
    XCR0 upper 32 bits valid bit field mask = 0x00000000
       XCR0 supported: x87 state            = true
       XCR0 supported: SSE state            = true
       XCR0 supported: AVX state            = true
       XCR0 supported: MPX BNDREGS          = false
       XCR0 supported: MPX BNDCSR           = false
       XCR0 supported: AVX-512 opmask       = false
       XCR0 supported: AVX-512 ZMM_Hi256    = false
       XCR0 supported: AVX-512 Hi16_ZMM     = false
       IA32_XSS supported: PT state         = false
       XCR0 supported: PKRU state           = false
    bytes required by fields in XCR0        = 0x00000340 (832)
    bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
 XSAVE features (0xd/1):
    XSAVEOPT instruction                        = true
    XSAVEC instruction                          = false
    XGETBV instruction                          = false
    XSAVES/XRSTORS instructions                 = false
    SAVE area size in bytes                     = 0x00000000 (0)
    IA32_XSS lower 32 bits valid bit field mask = 0x00000000
    IA32_XSS upper 32 bits valid bit field mask = 0x00000000
 AVX/YMM features (0xd/2):
    AVX/YMM save state byte size             = 0x00000100 (256)
    AVX/YMM save state byte offset           = 0x00000240 (576)
    supported in IA32_XSS or XCR0            = XCR0 (user state)
    64-byte alignment in compacted XSAVE     = false
 extended feature flags (0x80000001/edx):
    SYSCALL and SYSRET instructions        = true
    execution disable                      = true
    1-GB large page support                = true
    RDTSCP                                 = true
    64-bit extensions technology available = true
 Intel feature flags (0x80000001/ecx):
    LAHF/SAHF supported in 64-bit mode     = true
    LZCNT advanced bit manipulation        = true
    3DNow! PREFETCH/PREFETCHW instructions = false
 brand = "Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz"
 L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = 0x0 (0)
    data # entries            = 0x0 (0)
    data associativity        = 0x0 (0)
 L1 data cache information (0x80000005/ecx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L1 instruction cache information (0x80000005/edx):
    line size (bytes) = 0x0 (0)
    lines per tag     = 0x0 (0)
    associativity     = 0x0 (0)
    size (KB)         = 0x0 (0)
 L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
    instruction # entries     = 0x0 (0)
    instruction associativity = L2 off (0)
    data # entries            = 0x0 (0)
    data associativity        = L2 off (0)
 L2 unified cache information (0x80000006/ecx):
    line size (bytes) = 0x40 (64)
    lines per tag     = 0x0 (0)
    associativity     = 8-way (6)
    size (KB)         = 0x100 (256)
 L3 cache information (0x80000006/edx):
    line size (bytes)     = 0x0 (0)
    lines per tag         = 0x0 (0)
    associativity         = L2 off (0)
    size (in 512KB units) = 0x0 (0)
 Advanced Power Management Features (0x80000007/edx):
    temperature sensing diode      = false
    frequency ID (FID) control     = false
    voltage ID (VID) control       = false
    thermal trip (TTP)             = false
    thermal monitor (TM)           = false
    software thermal control (STC) = false
    100 MHz multiplier control     = false
    hardware P-State control       = false
    TscInvariant                   = true
 Physical Address and Linear Address Size (0x80000008/eax):
    maximum physical address bits         = 0x27 (39)
    maximum linear (virtual) address bits = 0x30 (48)
    maximum guest physical address bits   = 0x0 (0)
 Logical CPU cores (0x80000008/ecx):
    number of CPU cores - 1 = 0x0 (0)
    ApicIdCoreIdSize        = 0x0 (0)
 (multi-processing synth): multi-core (c=4)
 (multi-processing method): Intel leaf 0xb
 (APIC widths synth): CORE_width=4 SMT_width=1
 (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
 (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm

Som du kan se, så er der mange muligheder for at få oplysninger om hardwaren på din maskine.

  • cpu_hardware_information.txt
  • Sidst ændret: 2018/03/29 18:48
  • af snubbi